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Cap Multiplier for SMPS Convertir_en_PDF Version_imprimable Envoyer_par_mail
christophe Esperado : 24-04-2016
SMPS gives some advantages to power Linear audio power amplifiers. They are more efficient than traditional linear Power Supplies, they are a lot lighter, and some pretend they can sound better (My opinion too). This due to a better isolation from EMI/RFI from AC due to the reduced size of their transformer, with less capacitance between primary and secondary. And the high frequency of their switching frequency allowing the output capacitance to be recharged faster than the highest frequency you can hear..
Because nothing is perfect, we face some inconveniences. The first one is the leaking of this switching frequency, that you cannot eliminate totally, the second one is their internal resistance, that reduce slightly the output voltage when you ask high currents.
This project will try to ameliorate those two points without any regulation that use a feedback loop, and that many audiophiles pretend it affects the quality of the sound on any non class D amplifier: They tend to prefer the way they sound with a non regulated one. And they say they prefer the sound when you add a cap multiplier stage to a pure linear traditional supply. Image
We gone use the extra +-12V auxillarty voltages available on most of the SMPS, in order to get more margin to the command of the gate of the MOS FET and to power the pnp transistor with enough margin to avoid clipping.
Theory of the operation is very simple to understand. The Signal at the output of the SMPS (with added +12V) is filtered and regulated by the zeners and the cap, before to be applied to the transistor.
As we use the collector of this transistor, any decrease of the voltage on its base (the main output voltage drop of the SMPS)will increase the voltage on its collector in the opposite direction, compensating-it, decreasing the Drain/source resistance of the mosFET. Dynamically, but without any feedback loop. This voltage is applied to the command of an adjustable zener TL431, that stabilize the voltage applied to the gate of the power fet.
As-it, we reach more than 70/46dB of rejection of the switching frequency between 300mA and 7A of current in the load, as well as the 100HZ ripple from the SMPS that vary from -47 to -33dB at full load. And while the voltage of the SMPS vary from 67V to 63V when the current vary from 0 to 7A, at the output of the cap multiplier, the variation at the output will vary according to the image above from 60.3V to 60.5V:

(Clic on the image to see it full scale)
18.50W max power to dissipate from the FET @ 6.5A.

nb: The 800mV pp ripple values of the SMPS are totally fanciful, as Cresnet did not provided the real measurements to me, so, they are just there to see the rejection's values.

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